The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2022
Filed:
Jul. 30, 2020
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Scott David Huss, Cary, NC (US);
Loren B. Reiss, Raleigh, NC (US);
Christopher George Moscone, Cary, NC (US);
James Dennis Vandersand, Jr., Chapel Hill, NC (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); H04L 7/00 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0012 (2013.01); H03K 5/01 (2013.01); H04L 7/0091 (2013.01); H03K 2005/00058 (2013.01);
Abstract
Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.