Nonvolatile memory device having stacked cell transistors and operating method thereof

Abstract

A nonvolatile memory device includes a gate line extending in a first horizontal direction; a gate electrode of a pillar shape extending in a vertical direction from the gate line; a plurality of bit lines and a plurality of source lines extending in parallel in a second horizontal direction perpendicular to the first horizontal direction, the plurality of bit lines and the plurality of source lines being stacked in the vertical direction; and a plurality of cell transistors vertically stacked to surround an outer side surface of the gate electrode between the plurality of bit lines and the plurality of source lines. Each of the cell transistors includes a gate dielectric layer which surrounds the outer side surface of the gate electrode and a channel layer which surrounds an outer side surface of the gate dielectric layer.