The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Dec. 14, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Amit K. Srivastava, Folsom, CA (US);

Kenneth P. Foust, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01); G06F 13/364 (2013.01); G06F 2213/0016 (2013.01);
Abstract

In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.


Find Patent Forward Citations

Srivastava, Amit. (2022). System, apparatus and method for controlling duty cycle of a clock signal for a multi-drop interconnect (U.S. Patent No. 11226922). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11226922

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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