The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Oct. 09, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Noah Singer, White Plains, NY (US);

Daniele Di Genova, Hopewell Junction, NY (US);

Andrew Turner, Underhill, VT (US);

John Torok, Poughkeepsie, NY (US);

Gary Maier, Poughkeepsie, NY (US);

Richard Oldrey, Clintondale, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31718 (2013.01); G01R 31/3177 (2013.01); G01R 31/31713 (2013.01); G01R 31/31721 (2013.01);
Abstract

Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.


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