The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Dec. 21, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yoshiro Shimojo, Yokohama, JP;

Tomoya Sanuki, Suzuka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); G11C 16/04 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.


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