The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2022
Filed:
Apr. 03, 2020
University of Electronic Science and Technology of China, Chengdu, CN;
Ming Qiao, Chengdu, CN;
Linrong He, Chengdu, CN;
Yi Li, Chengdu, CN;
Chunlan Lai, Chengdu, CN;
Bo Zhang, Chengdu, CN;
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, Chengdu, CN;
Abstract
An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.