The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2022
Filed:
Jun. 19, 2020
Alpha and Omega Semiconductor International Lp, Sunnyvale, CA (US);
Yan Xun Xue, Los Gatos, CA (US);
Yueh-Se Ho, Sunnyvale, CA (US);
Long-Ching Wang, Cupertino, CA (US);
Xiaotian Zhang, San Jose, CA (US);
Zhiqiang Niu, Santa Clara, CA (US);
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP, Sunnyvale, CA (US);
Abstract
A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.