Holdup self-tests for power loss operations on memory systems

Abstract

Described herein is a system that includes a memory component and a processing device coupled to the memory component. The processing device identifies, in a test mode, a memory location of a memory component that is available to write test data, and detects a loss of power to the system while in the test mode. Responsive to detection of the loss of power, the processing device performs a continuous sequence of write operations to write the test data to the memory location using holdup energy until an amount of holdup energy is expended. After reboot of the system, the processing device determines a number of write operations successfully completed in the memory location by the continuous sequence of write operations before the amount of holdup energy is expended, and determines whether the number of write operations successfully completed satisfies a defect criterion. Responsive to the number of write operations successfully completed satisfying the defect criterion, the processing device reports a defect associated with the holdup energy.