The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
May. 26, 2020
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventor:
Bok Kyu Choi, Yongin-si Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/5381 (2013.01); H01L 23/5384 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06586 (2013.01);
Abstract
A stack package includes a lower semiconductor chip disposed on a package substrate, an interposer bridge including through vias, and an upper semiconductor chip. The upper semiconductor chip has a first edge and a second edge which are opposite to each other. The upper semiconductor chip includes a first region, a third region and a connection region which are located between the first and second edges. The upper semiconductor chip also includes a redistributed layer pattern that connects pads disposed on the first and third regions to each other. The redistributed layer pattern extends onto the connection region.