The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Mar. 23, 2021
Applicant:

Chung W. Ho, Taipei, TW;

Inventor:

Chung W. Ho, Taipei, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 21/4853 (2013.01); H01L 21/6835 (2013.01); H01L 23/145 (2013.01); H01L 23/5386 (2013.01); H01L 23/552 (2013.01); H01L 24/19 (2013.01); H01L 2221/68313 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.


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