The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Jan. 21, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yang Gyoo Jung, Hwaseong-si, KR;

Chul Woo Kim, Incheon, KR;

Hyo-Chang Ryu, Cheonan-si, KR;

Seung-Kwan Ryu, Seongnam-si, KR;

Yun Seok Choi, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/42 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01); H05K 1/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/42 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H05K 1/181 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06541 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.


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