The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
Sep. 26, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Vivek Kozhikkottu, Hillsboro, OR (US);
Suresh Chittor, Portland, OR (US);
Esha Choukse, Austin, TX (US);
Shankar Ganesh Ramasubramanian, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1045 (2016.01); G06F 12/06 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1054 (2013.01); G06F 11/3037 (2013.01); G06F 12/0207 (2013.01); G06F 12/0623 (2013.01); G06F 13/1689 (2013.01); G06F 2212/684 (2013.01);
Abstract
Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.