The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Sep. 30, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsien-Hsin Sean Lee, Duluth, GA (US);

William Wu Shen, Hsinchu, TW;

Yun-Han Lee, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G06F 12/0804 (2016.01); G11C 5/04 (2006.01); G11C 5/02 (2006.01); G06F 12/0891 (2016.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G06F 12/0891 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 7/22 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/45 (2013.01); G06F 2212/608 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.


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