The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
Mar. 27, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Martin Langhammer, Alderbury, GB;
Gregg William Baeckler, San Jose, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 7/53 (2006.01); G06N 20/00 (2019.01); G06F 7/544 (2006.01); G06F 30/34 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 7/5312 (2013.01); G06F 7/5306 (2013.01); G06F 7/5443 (2013.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06N 20/00 (2019.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract
A method for designing a system on a target device includes identifying a length for a carry chain that is supported by predefined quanta of a resource on the target device. A plurality of logical adders is mapped onto a single logical adder implemented on the carry chain subject to the identified length to increase logic utilization in a design for the system.