The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
Sep. 16, 2020
Gowin Semiconductor Corporation, GuangZhou, CN;
Jianhua Liu, Fremont, CA (US);
Jinghui Zhu, San Jose, CA (US);
Ning Song, Cupertino, CA (US);
Tianping Wang, Shanghai, CN;
Chienkuang Chen, Santa Clara, CA (US);
Diwakar Chopperla, Fremont, CA (US);
Tianxin Wang, Shanghai, CN;
Zhenyu Gu, Shanghai, CN;
Xiaozhi Lin, Shanghai, CN;
GOWIN Semiconductor Corporation, GuangZhou, CN;
Abstract
A field-programmable gate array ('FPGA') contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals ('RCSs') generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.