The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Aug. 12, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Wee Aun Jason Lim, Melaka, MY;

Paul Armand Asentista Calo, Melaka, MY;

Ting Soon Chin, Malacca, MY;

Chooi Mei Chong, Melaka, MY;

Sanjay Kumar Murugan, Malacca, MY;

Ying Pok Sam, Melaka, MY;

Chee Voon Tan, Seremban, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/28 (2006.01); H01L 21/00 (2006.01); H05K 7/18 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/84 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3135 (2013.01); H01L 23/495 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 23/49551 (2013.01); H01L 23/49838 (2013.01); H01L 24/29 (2013.01); H01L 24/30 (2013.01); H01L 24/32 (2013.01); H01L 24/38 (2013.01); H01L 24/40 (2013.01); H01L 24/83 (2013.01); H01L 2224/40175 (2013.01); H01L 2224/8484 (2013.01); H01L 2224/8492 (2013.01); H01L 2224/84801 (2013.01);
Abstract

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.


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