Burst clock control based on partial command decoding in a memory device

Abstract

Devices and methods include a command input configured to receive a command for a memory device. Second stage wakeup circuitry configured to receive a portion of the command and output an indication of whether the command is a non-burst command based on the portion. Clock gating circuitry is configured to receive an input clock and a wake signal. The clock gating circuitry is also configured to output an internal clock based at least in part on a pulse of the received wake signal. The clock gating circuitry also is configured to maintain the output of the internal clock for a duration based on the indication with the duration being shorter when the indication indicates that the command is a non-burst command.