The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2021
Filed:
May. 16, 2019
Applicant:
Huawei Technologies Co., Ltd., Shenzhen, CN;
Inventors:
Assignee:
HUAWEI TECHNOLOGIES CO., LTD., Shenzhen, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0891 (2016.01); G06F 12/0888 (2016.01); G06F 12/08 (2016.01); G06F 12/0879 (2016.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0673 (2013.01); G06F 12/08 (2013.01); G06F 12/0879 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0895 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/202 (2013.01); G06F 2212/608 (2013.01);
Abstract
A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.