The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Dec. 30, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Ravi Kiran Kandikonda, Frisco, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/4096 (2006.01); G06F 12/02 (2006.01); G11C 7/10 (2006.01); G11C 11/4072 (2006.01); G11C 11/408 (2006.01); G11C 11/4076 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 12/02 (2013.01); G11C 5/063 (2013.01); G11C 5/066 (2013.01); G11C 7/1072 (2013.01); G11C 11/4072 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01);
Abstract

A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.


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