The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Nov. 30, 2020
Applicant:

Stmicroelectronics International NV, Plan-les-Ouates, CH;

Inventors:

Vivek Mohan Sharma, New Delhi, IN;

Deepak Baranwal, Greater Noida, IN;

Amulya Pandey, Greater Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3193 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31703 (2013.01); G01R 31/3193 (2013.01); G01R 31/31713 (2013.01); G01R 31/31724 (2013.01); G06F 11/2215 (2013.01);
Abstract

A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.


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