The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

May. 10, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nachiket Desai, Portland, OR (US);

Harish Krishnamurthy, Beaverton, OR (US);

Suhwan Kim, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); H02M 1/14 (2006.01); H02M 3/158 (2006.01); H02M 3/157 (2006.01); H02M 3/15 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/1584 (2013.01); G06F 1/26 (2013.01); H02M 1/14 (2013.01); H02M 3/157 (2013.01); H02M 1/0032 (2021.05); H02M 3/1586 (2021.05);
Abstract

An apparatus is described which includes a delay-line with reasonably matched delay cells and some logic to ascertain both a correct number of DC-DC converters and interleaving angles or phase offsets. The apparatus measures an operating frequency in real-time in multiples of the individual delay cells of the delay-line. The smaller the period, the higher the load coupled to the DC-DC converters and, therefore the greater the number of DC-DC converters are needed to service the load. The period determines the load and can be used to determine the number of DC-DC converters needed and thereby accomplishing autonomous phase enabling/shedding.


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