The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Sep. 03, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventor:

Anirban Roy, Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/8242 (2006.01); H01L 21/20 (2006.01); H01L 27/24 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01); H01L 43/02 (2006.01); H01L 45/00 (2006.01); H01L 21/768 (2006.01); H01L 29/94 (2006.01); H01L 27/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/24 (2013.01); H01L 21/76877 (2013.01); H01L 27/0629 (2013.01); H01L 27/108 (2013.01); H01L 27/10829 (2013.01); H01L 27/222 (2013.01); H01L 29/407 (2013.01); H01L 29/945 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01L 45/06 (2013.01); H01L 45/16 (2013.01);
Abstract

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.


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