The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Mar. 13, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Sanjay Tiwari, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G06F 15/78 (2006.01); G06F 9/38 (2018.01); G11C 7/06 (2006.01); G06F 9/30 (2018.01); G11C 29/14 (2006.01); G11C 29/32 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 11/4096 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G06F 9/30029 (2013.01); G06F 9/30032 (2013.01); G06F 9/3877 (2013.01); G06F 9/3887 (2013.01); G06F 15/785 (2013.01); G11C 7/065 (2013.01); G11C 29/14 (2013.01); G11C 29/32 (2013.01); G11C 7/10 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G11C 16/10 (2013.01); Y02D 10/00 (2018.01);
Abstract

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.


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