The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Feb. 21, 2020
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Shinichi Kimoto, Tsukuba, JP;

Katsuhisa Tanaka, Tsukuba, JP;

Shinya Kyogoku, Yokohama, JP;

Ryosuke Iijima, Setagaya, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/12 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0869 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/41741 (2013.01); H01L 29/41775 (2013.01); H01L 29/66068 (2013.01); H01L 21/047 (2013.01);
Abstract

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.


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