The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Apr. 09, 2020
Applicant:

United Semiconductor (Xiamen) Co., Ltd., Fujian, CN;

Inventors:

Bin Guo, Singapore, SG;

Hailong Gu, Singapore, SG;

Chin-Chun Huang, Hsinchu County, TW;

Wen Yi Tan, Fujian, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76843 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate, patterning the first IMD layer to form first IMD patterns on the substrate, a trench surrounding the first IMD patterns, and a second IMD pattern surrounding the trench, forming a metal layer in the trench to surround the first IMD patterns, forming a second IMD layer on the first IMD patterns, the metal layer, and the second IMD pattern, and forming via conductors in the second IMD layer. Preferably, the via conductors not overlapping the first IMD patterns.


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