The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Mar. 01, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hiroaki Niimi, Cahoes, NY (US);

Pietro Montanini, Albany, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823468 (2013.01); H01L 21/76832 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/6653 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.


Find Patent Forward Citations

Loading…