The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Nov. 19, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Kyuseok Lee, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/408 (2006.01); G11C 11/409 (2006.01); G11C 7/22 (2006.01); G11C 11/4078 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G11C 7/222 (2013.01); G11C 11/409 (2013.01); G11C 11/4074 (2013.01); G11C 11/4078 (2013.01);
Abstract

A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.


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