The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Mar. 23, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Mark Van Dal, Linden, BE;

Gerben Doornbos, Kessel-Lo, BE;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 27/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/822 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/786 (2006.01); B82Y 10/00 (2011.01); H01L 29/775 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); B82Y 10/00 (2013.01); H01L 21/02236 (2013.01); H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0688 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/401 (2013.01); H01L 29/41725 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/6681 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78618 (2013.01); H01L 29/78654 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01);
Abstract

Semiconductor structures and methods for forming the same are provided. The method includes forming a fin structure over a substrate, and the fin structure includes alternately stacked semiconductor material layers and sacrificial layers. The method further includes forming a dummy gate structure, recessing the fin structure to form an opening, forming first source/drain spacers on sidewalls of the sacrificial layers by performing a first atomic layer deposition (ALD) process, and forming source/drain structure in the opening. The method further includes removing the dummy gate structure and the sacrificial layers to expose the semiconductor material layers and forming a gate structure wrapping around the semiconductor material layers.


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