The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Feb. 19, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Kenichi Kadota, Yokkaichi, JP;

Kazuhiro Nojima, Mie, JP;

Taro Shiokawa, Nagoya, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/11556 (2017.01); H01L 21/28 (2006.01); H01L 27/11565 (2017.01); H01L 21/311 (2006.01); H01L 27/11519 (2017.01); H01L 23/532 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/3065 (2006.01); H01L 21/306 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08); H01L 21/28568 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/764 (2013.01); H01L 23/53266 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 29/40114 (2019.08);
Abstract

According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.


Find Patent Forward Citations

Loading…