The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Aug. 23, 2019
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Amey Mahadev Walke, Heverlee, BE;

Liesbeth Witters, Lubbeek, BE;

Niamh Waldron, Heverlee, BE;

Robert Langer, Heverlee, BE;

Bernardette Kunert, Wilsele, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8258 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8258 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/31053 (2013.01); H01L 29/42316 (2013.01); H01L 29/66462 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.


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