The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Dec. 28, 2020
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Scott C. Best, Palo Alto, CA (US);

Ming Li, Fremont, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 5/04 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 25/18 (2006.01); H01L 23/48 (2006.01); G11C 11/406 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 5/02 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 11/406 (2013.01); G11C 11/4096 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01055 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/3011 (2013.01);
Abstract

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.


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