The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Sep. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Michael David Hutton, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 30/392 (2020.01); G06F 11/14 (2006.01); G06F 11/07 (2006.01); G06F 30/34 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); G06F 11/1417 (2013.01); G06F 30/34 (2020.01); G06F 2201/805 (2013.01);
Abstract

Systems and methods for detecting and managing errors in integrated circuits are provided. In one example, a system includes an integrated circuit that includes configuration memory that defines a circuit design implemented by the integrated circuit. The circuit design includes a plurality of regions. Additionally, the system is configured to determine a physical location of an error in the configuration memory and determine a location in a floorplan of the configuration memory that corresponds to the physical location of the error in the configuration memory. The floorplan identifies where the plurality of regions are defined in the configuration memory. The system is configured to determine in which of the plurality of regions the error in the configuration memory has occurred based at least in part on the location in the floorplan. Also, the system is configured to perform a corrective operation based on the location in the floorplan.


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