The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Dec. 06, 2018
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Mitchell G. Poplack, San Jose, CA (US);
Yuhei Hayashi, San Jose, CA (US);
Assignee:
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/331 (2020.01); G06F 30/34 (2020.01); G06F 30/39 (2020.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01);
U.S. Cl.
CPC ...
G06F 30/331 (2020.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/39 (2020.01); G06F 30/33 (2020.01);
Abstract
An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.