The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Dec. 16, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Loren B. Reiss, Raleigh, NC (US);

Scott David Huss, Cary, NC (US);

Fred Staples Stivers, Raleigh, NC (US);

James Dennis Vandersand, Jr., Chapel Hill, NC (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0008 (2013.01);
Abstract

A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.


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