The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Dec. 02, 2019
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventor:

Zhaoyao Zhan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); H01L 21/26513 (2013.01); H01L 21/26546 (2013.01); H01L 21/30604 (2013.01); H01L 21/30612 (2013.01); H01L 21/76224 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method of manufacturing a semiconductor device including following steps is provided. A substrate is provided. An ion implantation process is performed on the substrate to form doped material layers at different depth positions of the substrate and to define at least one nanowire layer. The at least one nanowire layer and the doped material layers are alternately stacked. A patterning process is performed on the at least one nanowire layer and the doped material layers to form at least one nanowire and doped layers. The at least one nanowire and the doped layers are alternately stacked to form a stack structure. A dummy gate structure spanning over the stack structure is formed. Spacers located on sidewalls of the dummy gate structure is formed. The dummy gate structure is removed to expose the at least one nanowire and the doped layers. The exposed doped layers are removed to form openings.


Find Patent Forward Citations

Zhan, Zhaoyao. (2021). Method of manufacturing semiconductor device (U.S. Patent No. 11189691). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11189691

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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