The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Oct. 23, 2019
Applicant:

J-devices Corporation, Usuki, JP;

Inventor:

Naoki Hayashi, Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24246 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82031 (2013.01); H01L 2224/82039 (2013.01); H01L 2224/92144 (2013.01); H01L 2224/92244 (2013.01);
Abstract

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.


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Hayashi, Naoki. (2021). Wiring substrate, semiconductor package having the wiring substrate, and manufacturing method thereof (U.S. Patent No. 11189553). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11189553

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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