The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
Nov. 13, 2019
Applicant:
Sandisk Technologies Llc, Addison, TX (US);
Inventors:
Assignee:
SanDisk Technologies LLC, Addison, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G11C 7/14 (2006.01); G11C 11/4094 (2006.01); H01L 27/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/56 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G11C 7/14 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/5635 (2013.01); H01L 27/0688 (2013.01);
Abstract
A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.