The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
Sep. 23, 2019
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Sang-Chi Huang, Hsinchu, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Jung-Chan Yang, Longtan Township, TW;
Pochun Wang, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of forming an integrated circuit includes generating a first and a second standard cell layout design, generating a first set of cut feature layout patterns extending in a first direction, and manufacturing the integrated circuit based on the first or second standard cell layout design. Generating the first standard cell layout design includes generating a first set of conductive feature layout patterns extending in the first direction, and overlapping a first set of gridlines extending in the first direction. Generating the second standard cell layout design includes generating a second set of conductive feature layout patterns extending in the first direction and overlapping a second set of gridlines extending in the first direction. A side of a first cut feature layout pattern extending in the first direction is aligned with a first gridline of the first or second set of gridlines.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile