The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Aug. 08, 2018
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Dmitry Korchemny, Kfar Saba, IL;

Ashok Kumar Bhatt, Uttar Pradesh, IN;

Eduard Rudolf Cerny, Worcester, MA (US);

Hanish Singla, Uttar Pradesh, IN;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/331 (2020.01); G06F 30/3323 (2020.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/331 (2020.01); G06F 30/3323 (2020.01);
Abstract

Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.


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