The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Feb. 01, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chien-Ti Hou, Taichung, TW;

Wu-Chuan Cheng, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01); G06F 9/355 (2018.01); G06N 3/08 (2006.01); G06N 3/04 (2006.01); G06N 3/063 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3893 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/3557 (2013.01); G06F 9/544 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01);
Abstract

A memory apparatus and an operation method thereof are provided. The memory apparatus includes a mode configuration register, a system memory array, a pointer and an arithmetic circuit including logic operation units. The mode configuration register stores weight matrix information and a base address. The system memory array stores feature values in a feature map from the base address according to the weight matrix information. The pointer stores the base address and a weight matrix size to provide pointer information. The arithmetic circuit sequentially or parallelly reads the feature values according to the pointer information. The arithmetic circuit parallelly arranges weight coefficients of a selected weight matrix and the corresponding feature values in each of the corresponding logic operation units according to the weight matrix information, and causes the logic operation units to perform computing operations parallelly to output intermediate layer feature values to an external processing unit.


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