The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
Mar. 26, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jeffrey J. Cook, Portland, OR (US);
Srikanth T. Srinivasan, Portland, OR (US);
Jonathan D. Pearce, Hillsboro, OR (US);
David B. Sheffield, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3842 (2013.01); G06F 9/30043 (2013.01); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06F 9/384 (2013.01);
Abstract
In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.