The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Sep. 06, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Praveen Mosalikanti, Portland, OR (US);

Nasser Kurd, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01); H03L 2207/06 (2013.01); H03L 2207/50 (2013.01);
Abstract

An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.


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