The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Nov. 21, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yoshinori Tanaka, Kanagawa, JP;

Wei-Che Chang, Taichung, TW;

Kai Jen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10885 (2013.01); G11C 5/063 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); H01L 27/1085 (2013.01); H01L 27/10823 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01);
Abstract

A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.


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