The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Dec. 06, 2019
Applicant:

Gan Systems Inc., Ottawa, CA;

Inventors:

Juncheng Lu, Kanata, CA;

Di Chen, Ottawa, CA;

Larry Spaziani, Chelmsford, MA (US);

Peter Anthony Di Maso, Ottawa, CA;

Assignee:

GaN Systems Inc., Ottawa, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 25/11 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 23/49811 (2013.01); H01L 23/5386 (2013.01); H01L 25/115 (2013.01); H01L 29/2003 (2013.01); H01L 29/7786 (2013.01);
Abstract

Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.


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