The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Aug. 18, 2017
Applicant:

Suss Microtec Lithography Gmbh, Garching, DE;

Inventors:

Hale Johnson, Jericho, VT (US);

Gregory George, Colchester, VT (US);

Aaron Loomis, Huntington, VT (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/687 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67092 (2013.01); H01L 21/6719 (2013.01); H01L 21/67742 (2013.01); H01L 21/67748 (2013.01); H01L 21/6838 (2013.01); H01L 21/68707 (2013.01); H01L 21/68721 (2013.01); H01L 21/68728 (2013.01); H01L 21/68742 (2013.01); H01L 21/68771 (2013.01); H01L 24/75 (2013.01); H01L 24/80 (2013.01); H01L 24/94 (2013.01); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/757 (2013.01); H01L 2224/7531 (2013.01); H01L 2224/7565 (2013.01); H01L 2224/75101 (2013.01); H01L 2224/75251 (2013.01); H01L 2224/75252 (2013.01); H01L 2224/75301 (2013.01); H01L 2224/75305 (2013.01); H01L 2224/75312 (2013.01); H01L 2224/75701 (2013.01); H01L 2224/75702 (2013.01); H01L 2224/75703 (2013.01); H01L 2224/75743 (2013.01); H01L 2224/75754 (2013.01); H01L 2224/80203 (2013.01); H01L 2224/80907 (2013.01); H01L 2224/94 (2013.01);
Abstract

An industrial-scale system and method for handling precisely aligned and centered semiconductor substrate (e.g., wafer) pairs for substrate-to-substrate (e.g., wafer-to-wafer) aligning and bonding applications is provided. Some embodiments include an aligned substrate transport device having a frame member and a spacer assembly. The centered semiconductor substrate pairs may be positioned within a processing system using the aligned substrate transport device, optionally under robotic control. The centered semiconductor substrate pairs may be bonded together without the presence of the aligned substrate transport device in the bonding device. The bonding device may include a second spacer assembly which operates in concert with that of the aligned substrate transport device to perform a spacer hand-off between the substrates. A pin apparatus may be used to stake the substrates during the hand-off.


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