The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Apr. 28, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Jiann-Horng Lin, Hsinchu, TW;

Chao-Kuei Yeh, Changhua County, TW;

Ying-Hao Wu, Taoyuan, TW;

Tai-Yen Peng, Hsinchu, TW;

Chih-Hao Chen, Hsinchu, TW;

Chih-Sheng Tian, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/0274 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76805 (2013.01); H01L 21/76811 (2013.01);
Abstract

According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.


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