The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Dec. 18, 2020
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Ram Sivaramakrishnan, San Jose, CA (US);

Sumti Jairath, Santa Clara, CA (US);

Emre Ali Burhan, Sunnyvale, CA (US);

Manish K. Shah, Austin, TX (US);

Raghu Prabhakar, San Jose, CA (US);

Ravinder Kumar, Fremont, CA (US);

Arnav Goel, San Jose, CA (US);

Ranen Chatterjee, Fremont, CA (US);

Gregory Frederick Grohoski, Bee Cave, TX (US);

Kin Hing Leung, Cupertino, CA (US);

Dawei Huang, San Diego, CA (US);

Manoj Unnikrishnan, Saratoga, CA (US);

Martin Russell Raumann, San Leandro, CA (US);

Bandish B. Shah, San Francisco, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 11/26 (2006.01); G06F 9/54 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 11/26 (2013.01); G06F 9/547 (2013.01); G06F 11/2236 (2013.01); G06F 11/2268 (2013.01); G06F 15/7871 (2013.01);
Abstract

A data processing system comprises a plurality of reconfigurable processors including a first reconfigurable processor and additional reconfigurable processors, a plurality of buffers in a shared memory accessible to the first reconfigurable processor and the additional reconfigurable processors, and runtime logic configured to execute one or more configuration files for applications using the first reconfigurable processor and the additional reconfigurable processors. Execution of the configuration files includes receiving data from the first reconfigurable processor and providing the data to at least one of the additional reconfigurable processors, and receiving data from the at least one of the additional reconfigurable processors and providing the data to the first reconfigurable processor.


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