The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2021
Filed:
Dec. 18, 2020
Sambanova Systems, Inc., Palo Alto, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Emre Ali Burhan, Sunnyvale, CA (US);
Manish K. Shah, Austin, TX (US);
Raghu Prabhakar, San Jose, CA (US);
Ravinder Kumar, Fremont, CA (US);
Arnav Goel, San Jose, CA (US);
Ranen Chatterjee, Fremont, CA (US);
Gregory Frederick Grohoski, Bee Cave, TX (US);
Kin Hing Leung, Cupertino, CA (US);
Dawei Huang, San Diego, CA (US);
Manoj Unnikrishnan, Saratoga, CA (US);
Martin Russell Raumann, San Leandro, CA (US);
Bandish B. Shah, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
The technology disclosed relates to buffer-based inter-node streaming of configuration data over a network fabric. In particular, the technology disclosed relates to a runtime processor configured to load and execute a first subset of configuration files in a set of configuration files on a first reconfigurable processor operatively coupled to a first processing node, load and execute a second subset of configuration files in the set of configuration files on a second reconfigurable processor operatively coupled to a second processing node, and use a first plurality of buffers operatively coupled to the first processing node, and a second plurality of buffers operatively coupled to the second processing node to stream data between the first reconfigurable processor and the second reconfigurable processor to load and execute the first subset of configuration files and the second subset of configuration files.