The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Apr. 22, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Jun Liu, San Jose, CA (US);

Bruce Young, Gilroy, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H03K 3/0375 (2013.01);
Abstract

A master latch includes a latch input node and a latch output node, a first inverter with an input and an output, the input coupled to the latch input node and the output coupled to the latch output node, and a second inverter with an input and an output, the input coupled to the latch output node and the output coupled to the latch input node. The master latch further includes a first pull-up device connected between a source voltage and the latch input node, the first pull-up device configured to pull the latch input node up towards the source voltage when the latch output node is low, and a first pull-down device connected between the latch input node and a ground voltage, the first pull-down device configured to pull the latch input node towards the ground voltage when the latch output node is high.


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