The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11177437 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 16, 2021

Filed:

Nov. 15, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hao Tang, Slingerlands, NY (US);

Michael Rizzolo, Delmar, NY (US);

Injo Ok, Loudonville, NY (US);

Theodorus E. Standaert, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 23/544 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/16 (2013.01); H01L 23/544 (2013.01); H01L 27/2463 (2013.01); H01L 45/1253 (2013.01); H01L 2223/54426 (2013.01);
Abstract

An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.


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Tang, Hao. (2021). Alignment through topography on intermediate component for memory device patterning (U.S. Patent No. 11177437). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11177437

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